This invention relates generally to an information processing apparatus such as a digital signal processor and more particularly to a technique which is effective for improving the speed of address calculation by reducing the number of program steps.
Apparatuses for quantizing an audio signal or a video signal and making a digital arithmetic operation or conversion operation of the digital signal obtained by analog-to-digital conversion of the quantized signal are generally referred to as "digital signal processors".
The operations of the digital signal processors include filtering, equalization, reduction of noise and echo, modulation, Fourier transform, extraction of characteristic parameters of the signal, signal prediction, emphasis of the video signal, and so forth.
The output signal from the digital signal processor is returned to an analog signal through digital-analog conversion and a final output signal is obtained through a low-pass filter.
In the 1970s, the progress in LSI technique proposed exclusive-use LSIs in which adders, multipliers, unit delay elements and the like as the basic constituent elements of digital arithmetic processing were laid out along the flow of signal processing. Since this exclusive-use LSI can minimize a circuit scale, it would be most economical if it could be mass-produced.
In the 1980s, on the other hand, digital signal processor LSIs of a stored program control type were proposed. Since this LSI programs the algorithm of signal processing by micro-instruction and reads out and executes this instruction from a memory, it has a multi-use property or versatility in that any signal processing can be accomplished in accordance with a program.
The present invention relates to a technique which is suitable for the multi-use digital signal processor LSI of the kind described above.
The digital signal processor LSI examined by the present inventors before filing of the present Application consists of a data memory 11 for storing data, an instruction memory 12 for storing instruction codes, an address arithmetic unit 13 for calculating the access address for the data memory 11, a program counter 14 for designating the access address of the instruction memory 12, a data arithmetic unit 15 for calculating the data that is read out from the data memory 11, a decoder 16 for decoding the instruction read out from the instruction memory 12, and the like, as shown in FIG. 9 of the accompanying drawings. In LSI, these circuits 11 to 16 are built in one semiconductor chip.
First of all, one instruction is read out from the address of the instruction memory 12 which is designated by the program counter 14 and is decoded by the decoder 16 to determine the address which is to be read out next. The address is sent to the program counter 14 and the address for reading the operand data to be calculated is calculated by the address arithmetic unit 13. The operand data is read out by making access to the data memory 11 by the address thus calculated, and is then inputted to the data arithmetic unit 15 for calculation processing.
Hereinafter, the address arithmetic unit 13 shown in FIG. 9 will be described in further detail. The address arithmetic unit disposed in the digital signal processor examined before the filing of the present Application consists of an arithmetic unit 104 and several registers 102, 107 as shown in FIG. 2. Whenever it receives the instruction, the address arithmetic unit 13 performs predetermined calculation and outputs the result of calculation as the address. Such a construction is the same as that of the data arithmetic unit 15 shown in FIG. 9. This construction has high versatility and can be said suitable for data arithmetic units for performing various calculations. However, the most characterizing feature of address calculation lies in its algorithm and its major proportion mostly consists of repetition of the same calculation.
Where the data memory stores the coefficients of the digital filter, for example, access is made sequentially and repeatedly to a certain predetermined address range of the memory for filtering and the coefficient data of the filter are sent to the data arithmetic unit at fixed periods. The calculation made by the address arithmetic unit 104 at this time is only repetition of loading of the initial address and increment (+1) calculation.
FIG. 10(b) shows an example of the weigh function obtained by converting time- and space-wise the predetermined frequency characteristics of the digital filter. In the diagram, the abscissa represents the time and the ordinate does a signal transmission amount. If the time width is secured infinitely, the filter characteristics will become completely ideal but this is impossible in practice. It is therefore one of the most important design items of digital filters to set the time width to a definite value n+1 (hereinafter called the "tap number") within a range in which an error from the ideal value is permissible.
Therefore, the weight function waveform such as shown in FIG. 10(b) is cut in a strip shape and stored in the addresses 0 to n of the memory such as shown in FIG. 10(a) as the filtering coefficients. The digital coefficients thus stored are sequentially read out from the memory and sequentially subjected to the product and/or sum operation by the data arithmetic unit with the digital input signals that are sequentially inputted after quantization and analog-digital conversion. Digital signal processing is carried out in this manner.
The number of repetition m of the n+1 step product and/or sum operation necessary for signal processing of the digital signal processor described above is defined as the "number of times of filtering or filtering number".
FIG. 3 shows the operation flowchart of the address arithmetic unit shown in FIG. 2. Here, the number of times of repetition of operations is loop 1 (=m), the tap number (the number of each time point cut out in the stripe shape) is loop 2 (=n) and reduction count is made sequentially from these values.
First of all, the initial value 0 is set to the register 102 (step 31) and then the number of times of operations in filtering is set (loop 1=m; step 32). Next, the initial value 0 is passed from the register 102 to the arithmetic unit 104 and loaded to the register 107 (step 33) and its value is set as the initial address output (step 34). Next, the number obtained by subtracting 1 from the tap number of the filter is set as the second loop. In other words, since one tap has been complete at the time when the initial address value is outputted, the remaining number n is set (step 35). The increment calculation instruction and the address output are executed inside this second loop. In other words, the initial address output 0 and the value 1 set to the register 102 are added by the arithmetic unit 104 and the result (0+1) is set to the register 107 and outputted (steps 36, 37). When the second loop is complete (or when the value of the loop 2 is subtracted and reaches 0), the flow returns again to the first loop and the procedures from loading of the initial value address are repeated (step 38). When the result does not turn out 0 even when the value of the loop 2 is subtracted by 1, the procedure is repeated, the procedure returns to the step 33 and the initial value address is loaded (steps 40, 41).
FIG. 4 shows an example of the program used when executing the flowchart shown in FIG. 3 by the construction shown in FIG. 2. In other words, the program includes the instruction of setting the initial value address 0 to the register 1 (step 1), the instruction of setting the loop 1 to 1 - m (step 2), the instruction of loading the content of the register 1 to the register 3 (step 3), the instruction of outputting the content of the register 3 (step 4), the instruction of setting the loop 2 to 1 - n (step 5), the instruction of incrementing the register 3 (step 6), the instruction of outputting the register 3 (step 7), the instruction of executing the next loop 2 (step 8), the instruction of executing the next loop 1 (step 9), and the like.
In accordance with the construction shown in FIG. 2, the loop is double as shown in FIG. 4. In other words, the inner loop number setting instruction (the instruction of step 5 in FIG. 4) must be executed whenever one filtering is complete and for this reason, a processing speed drops.
On the other hand, address computation units to support modulo addressing were proposed in "0n the IC Architecture and Design of a 2 .mu.m CMOS 8 MIPS Digital Signal Processor with Parallel Processing Capability: The PCB 5010/5011" (PROCEEDINGS ICASSP 86, Vol. 1, p.p. 385-388) at Seccison 8-1 of Tokyo Conference of 1968 ICASSP.
As the address value starts from the initial value address (0 address) of the output of the address arithmetic unit, the access address increases sequentially due to increment (+1), then arrives at the final value address and exceeds this final value address, modulo addressing detects the excess of the address value beyond the final value address and automatically returns the address value to the initial value address (0 address) on the basis of this detection result.
In accordance with this method, therefore, the loop can be reduced to a single loop but the tap number of the filter must be limited to the power of 2, and the method involves the problem in that its versatility is extremely low.